1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a method and apparatus for driving a liquid crystal display wherein a picture quality can be clearly kept upon conversion of a resolution mode of the liquid crystal display.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) of active matrix driving system uses thin film transistors (TFT's) as switching devices to display a natural moving picture. Since such a LCD can be made into a smaller device in size than the existent Brown tube, it has been widely used for a computer monitor well as office automation equipment such as a copy machine, etc. and portable equipment such as a cellular phone and a pager, etc.
Such a LCD trends toward a high resolution and a large-scale screen. Recently, a liquid crystal monitor of a personal computer has supported resolutions required for high-class equipment such as a workstation. FIG. 1 schematically shows such a LCD.
Referring to FIG. 1, the LCD includes a liquid crystal display panel 2 having TFT's and liquid crystal cells provided between gate lines GL1 to GLm and data lines DL1 to DLn, a source drive integrated circuit (IC) 6 for supplying a data to the data lines DL1 to DLn, a gate drive IC for sequentially applying scanning pulses to the gate lines GL1 to GLm, a timing controller 8 for applying required timing control signals to the source drive IC 6 and the gate drive IC 4, and an interface circuit 12 for supplying a data from a graphic card (not shown) to the timing controller 8.
The source drive IC 6 samples and latches red (R), green (G) and blue (B) data in response to a source shift clock (SSC) from the timing controller to convert a timing system of ‘dot at a time scanning’ into that of ‘line at a time scanning’. The data converted into a system of ‘line at a time scanning’ is synchronized with the scanning pulses and simultaneously applied to n data lines DL1 to DLn.
Timing control signals applied from the timing controller 8 to the source drive IC 6 include a source start pulse (SSP) for instructing an initiation of a data sampling or latch in one horizontal synchronization interval, a source output enable signal (SOE) for controlling an output of the source drive IC 6 and a polarity control signal (POL) for inverting the polarity of a data upon frame/line/column inversion driving, etc. besides the SSC.
The gate drive IC 6 includes a shift register and a level shifter, etc. The gate driver IC 6 sequentially applies scanning pulses having a gate high voltage in response to a gate start pulse (GSP) from the timing controller 8, to thereby charge a data in the liquid crystal cells.
Timing control signals applied from the timing controller 8 to the gate drive IC 4 include a gate shift clock GSC for determining a time when the gate of the TFT is turned on or off and a gate output enable signal (GOE) for controlling an output of the gate drive IC 4, etc. besides the GSP.
The timing controller 8 receives RGB signals inputted via the interface circuit 12 to distribute it into the source drive IC 6 and control the source drive IC 6 and the gate drive IC 4. The timing controller 8 generates the timing control signals required for the source drive IC 6 and the gate drive IC 4 using the SSC applied from a reference clock generator (not shown).
The interface circuit 12 applies RGB data, a data enable signal I_DE and a dot clock Dclk from the graphic card (not shown) to the timing controller 8.
The timing controller 8 and the interface circuit 12 may include a LVDS circuit so that they can reduce the number of data supply lines and an electromagnetic interference.
The VESA (Video Electronics Standard Association) has defined the number of dot clocks Dclk having a frequency of 65 Mhz at a blanking interval (or a low logic interval) of a data enable signal I_DE inputted from the graphic card to the timing controller 8 in resolution modes of UXGA, SXGA, XGA, SVGA and VGA by an even number. However, if the resolution mode is converted from UXGA, SXGA or XGA into SVGA or VGA, the number of dot clocks Dclk is changed into an odd number. When the resolution mode is converted, a horizontal noise emerges on the screen.
As can be seen from FIG. 2, the conventional timing controller 8 toggles a dot clock Dclk from the interface circuit 12 irrespectively of a resolution conversion of the graphic card to generate the SSC. More specifically, the conventional timing controller 8 operates a reset circuit at a dot clock Dclk generated at the third sequence from a time when the data enable signal I_DE is changed into a high level independently of a resolution to reset a source shift clock SSC. Herein, as shown in FIG. 3, if a resolution mode is UXGA, SXGA or XGA, the number of dot clocks Dclk (65 Mhz in the XGA mode) at a blanking interval of the data enable signal I_DE is an even number (n). In this case, the source shift clock SSC has normal waveform and frequency. On the other hand, as shown in FIG. 4, if a resolution mode is SVGA or VGA, the number of dot clocks Dclk at a blanking interval of the data enable signal DE is changed into an odd number. As a result, when the resolution mode is converted from UXGA, SXGA or XGA into SVGA or VGA, the source start pulse SSP and the source shift clock SSC inputted to the source shift clock SSC go beyond a timing specification stipulating a set-up time and a hold time to cause a horizontal noise on the screen, as shown in FIG. 5.
In FIG. 3 to FIG. 5, the data enable signal DE is created by an internal circuit of the timing controller 8 to instruct a sampling initiation time of an odd data and an even data divided from an input data by means of the timing controller 8. This can be more easily understood from waveform diagrams of FIG. 9A to FIG. 11B capturing a scope screen. In the waveform diagrams of FIGS. 9A to 11B, the horizontal axis represents a time (i.e., 25.0 ns unit), and the vertical axis does a voltage (i.e., 2.0V unit).
As can be seen from FIG. 9A and FIG. 9B that represent waveforms of a source start pulse SSP and a source shift clock SSC at the set-up time and the hold time in a resolution of XGA, since the number of dot clocks Dclk in a resolution of XGA is an even number, waveforms of the source start pulse SSP and the source shift clock SSC take a normal shape. On the other hand, as can be seen from FIG. 10A and FIG. 10B that represent waveforms of the source start pulse SSP and the source shift clock SSC at the set-up time and the hold time when a resolution is converted from XGA into VGA, since the number of dot clocks Dclk is changed from an even number into an odd number, a period of the source shift clock SSC is changed to distort a waveform of the source shift clock SSC at a conversion time of resolution. FIG. 11A and FIG. 11B shows an overlapped state of waveforms of the source start pulse SSP and the source shift clock SSC at a time when an XGA resolution is sustained and at a time when a resolution mode is converted from XGA into VGA, respectively.